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mt9m001: 1/2-inch megapixel digital image sensor features mt9m001_ds rev. m pub. 5/15 en 1 ?semiconductor components industries, llc , 1/2-inch megapixel cmos digital image sensor mt9m001c12stm (monochrome) datasheet, rev. m for the latest datasheet, please visit www.onsemi.com features ? array format (5:4): 1,280h x 1,024v (1,310,720 active pixels). total (incl. dark pixels): 1,312h x 1,048v (1,374,976 pixels) ? frame rate: 30 fps progressive scan; programmable ? shutter: electronic rolling shutter (ers) ? window size: sxga; programmable to any smaller format (vga, qvga, cif, qcif, etc.) ? programmable controls: gain, frame rate, frame size applications ? digital still cameras ? digital video cameras ?pc cameras general description the on semiconductor mt9m001 is an sxga-format with a 1/2-inch cmos active-pixel digital image sen- sor. the active imaging pixel array of 1,280h x 1,024v. it incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. it is programmable through a simple two-wire serial interface. this megapixel cmos image sensor features on semi- conductor?s breakthrough low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. table 1: key performance parameters the sensor can be operated in its default mode or pro- grammed by the user for frame size, exposure, gain set- ting, and other parameters. the default mode outputs an sxga-size image at 30 fr ames per second (fps). an on-chip analog-to-digital co nverter (adc) provides 10 bits per pixel. frame_valid and line_valid signals are output on dedicated pins , along with a pixel clock that is synchronous with valid data. parameter value optical format 1/2-inch (5:4) active imager size 6.66 mm (h) x 5.32 mm (v) active pixels 1,280 h x 1,024 v pixel size 5.2 ? m x 5.2 ? m shutter type electronic rolling shutter (ers) maximum data rate/ master clock 48 mps/48 mhz frame rate sxga (1280 x 1024) 30 fps progressive scan; programmable adc resolution 10-bit, on-chip responsivity 2.1 v/lux-sec dynamic range 68.2 db snr max 45 db supply voltage 3.0 v ? 3.6 v, 3.3 v nominal power consumption 363 mw at 3.3 v (operating); 294 ? w (standby) operating temperature 0c to +70c packaging 48-pin clcc
mt9m001_ds rev. m pub. 5/15 en 2 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9m001c12stm-dp 1 mp 1/2" cis dry pack with protective film mt9m001c12stm-dr 1 mp 1/2" cis dry pack without protective film mt9m001c12stm-dr1 1 mp 1/2" cis dry pack single tray without protective film mt9m001c12stm-tp 1 mp 1/2" cis tape & reel with protective film mt9m001c12stm-tr 1 mp 1/2" cis tape & reel without protective film MT9M001D00STMC84AC1-200 1 mp 1/2" cis die sales, 200 ? m thickness
mt9m001_ds rev. m pub. 5/15 en 3 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor table of contents table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 two-wire serial interface sample write and read seq uences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
mt9m001_ds rev. m pub. 5/15 en 4 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor list of figures list of figures figure 1: 48-pin clcc package pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: pixel pattern detail (top right co rner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 7: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 8: timing diagram showing a write to reg0x09 with the va lue 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 9: timing diagram showing a read from reg0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .15 figure 10: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 11: readout of six columns in norm al and column mirror output mode . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: readout of six rows in normal and row mirror output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 13: readout of eight pixels in norm al and column skip output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14: black level calibration flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: general timing for snapshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 16: different line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 17: data output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 18: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 19: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 20: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 21: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 22: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 23: acknowledge signal timing after an 8-bit read from the sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 24: quantum efficiency?mon ochrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 25: image center offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 26: optical orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 27: 48-pin clcc package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
mt9m001_ds rev. m pub. 5/15 en 5 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: frame time?long integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: recommended gain settings at 48 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 7: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 8: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 9: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 10: optical area dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
mt9m001_ds rev. m pub. 5/15 en 6 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor general description general description figure 1: 48-pin clcc package pinout diagram 1 2 3 4 5 6 48474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 standby trigger nc reset# nc nc oe# nc a gnd v aa a gnd a gnd nc frame_valid line_valid strobe d gnd v dd d out <9> d out <8> d out <7> d out <6> d out <5> pixclk nc v aa a gnd v dd d gnd d out <0> d out <1> d out <2> d out <3> d out <4> clkin nc nc d gnd v dd nc nc vaapix a gnd a gnd sclk s data nc d gnd
mt9m001_ds rev. m pub. 5/15 en 7 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor general description figure 2: block diagram clock two-wire serial input/output 10-bit data sync signals control register analog processing active-pixel sensor (aps) array sxga 1,280h x 1,024v timing and control adc
mt9m001_ds rev. m pub. 5/15 en 8 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor general description table 3: pin descriptions pin numbers symbol type description 29 clkin input clock in. master clock into sensor (48 mhz maximum). 13 oe# input output enable. oe# when high places outputs d out <0:9>, frame_valid, line_valid, pixclk, and strobe into a tri-state configuration. 10 reset# input reset. activates (low) asynchronous reset of sensor. all registers assume factory defaults. 46 sclk input serial clock. clock for serial interface. 7 standby input standby. activates (high) standby mode, disables analog bias circuitry for power saving mode. 8 trigger input trigger. activates (high) snapshot sequence. 45 s data input/output serial data. serial data bus, requires 1.5 k ? resistor to 3.3v for pull-up. 24C28, 32C36 d out <0C9> output data out. pixel data output bits 0:9, d out <9> (msb), d out <0> (lsb). 41 frame_valid output frame valid. output is puls ed high during frame of valid pixel data. 40 line_valid output line valid. output is pulsed h igh during line of selectable valid pixel data (see reg0x20 for options). 31 pixclk output pixel clock. pixel data outputs are valid during falling edge of this clock. frequency = (master clock). 39 strobe output strobe. output is pulsed high to indicate sensor reset operation of pixel array has completed. 15,17,18,21, 47, 48 a gnd supply analog ground. provide isolated ground for analog block and pixel array. 5, 23, 38, 43 d gnd supply digital ground. provide isol ated ground for digital block. 16, 20 v aa supply analog power. provide power supply for analog block, 3.3v 0.3v. 1 vaapix supply analog pixel power. provide power supply for pixel array, 3.3v 0.3v (3.3v). 4, 22, 37 v dd supply digital power. provide power supply for digital block, 3.3v 0.3v. 2, 3 ,6, 9, 11, 12,14, 19, 30, 42, 44 nc no connect. these pins must be left unconnected.
mt9m001_ds rev. m pub. 5/15 en 9 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor pixel data format pixel data format pixel array structure the mt9m001 pixel array is configured as 1,312 columns by 1,048 rows (shown in figure 3). the first 16 columns and the first ei ght rows of pixels are optically black, and can be used to monitor the black level. the la st seven columns and the last seven rows of pixels are also optically black. the black row data is used internally for the automatic black level adjustment. however, the black rows can also be read out by setting the sensor to raw data output mode (reg0x20, bit 11 = 1). there are 1,289 columns by 1,033 rows of optically active pixels, which provides a four-pixel boundary around the sxga (1,280 x 1,024) image. figure 3: pixel array description figure 4: pixel pattern detail (top right corner) note: e = even column or row 0 = odd column or row (1311, 1047) 16 black columns 7 black rows 8 black rows (0, 0) 7 black columns sxga (1,280 x 1,024) + 4 pixel boundary + additional active column + additional active row = 1,289 x 1,033 active pixels pixel (8, 16 ) black pixe ls column readout direction . . . ... row readout d irection ee oe ee oe ee oe eo oo eo oo eo oo ee oe ee oe ee oe eo oo eo oo eo oo ee oe ee oe ee oe eo oo eo oo eo oo ee oe ee oe ee oe
mt9m001_ds rev. m pub. 5/15 en 10 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor pixel data format output data format the mt9m001 image data is read out in a progressive scan. valid image data is surrounded by horizontal blanking and ve rtical blanking, as shown in figure 5. the amount of horizontal blanking and vertical blanking is programmable through reg0x05 and reg0x06, respectively. line_valid is high during the shaded region of the figure. frame_valid timing is described in ?output data timing? on page 10. figure 5: spatial illustration of image readout output data timing the data output of the mt9m001 is synchronized with the pixclk output. when line_valid is high, one 10-bit pixel datum is output every pixclk period. figure 6: timing example of pixel data the rising edges of the pixclk signal are nominally timed to occur on the rising d out edges. this allows pixclk to be used as a clock to latch the data. d out data is valid on the falling edge of pixclk. the pixclk is high while master clock is high and then low while master clock is low. it is continuously enabled, even during the blanking period. the parameters p1, a, p2, and q in figure 7 are defined in table 4. p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking line_valid pixclk d out 9-d out 0 . . . . . . . . . . . . . . . . p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blankin g
mt9m001_ds rev. m pub. 5/15 en 11 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor pixel data format figure 7: row timing and frame_valid/line_valid signals p1 a q a q ap2 . . . . . . . . . number of master clocks frame_valid line_valid
mt9m001_ds rev. m pub. 5/15 en 12 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor pixel data format frame timing formulas notes: 1. row skip mode should have no effect on the integration time. column skip mode changes the effec- tive value of column size (reg0x04) as follows: column skip 2 => r4eff = (int(r4 / 4) x 2) + 1 column skip 4 => r4eff = (int(r4 / 8) x 2) + 1 column skip 8 => r4eff = (int(r4 / 16) x 2) + 1 where the int() function truncates to the next lowe st integer. now use r4eff in the equation for row time instead of r4 2. default for reg0x05 = 9. however, sensor ignores any value for reg0x05 less than 19. sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to figure 6). the recommended master clock frequency is 48 mhz. the vertical blank and total frame time equations assume that the number of in tegration rows (bits 13 through 0 of reg0x09) is less than the numb er of active plus blanking rows (reg0x03 + 1 + reg0x06 + 1). if this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in table 5. table 4: frame timing parameter name equation (master clock) default timing notes a active data time (reg0x04 + 1) 1,280 pixel clocks = 26.7 ? s 1 p 1 frame start blanking (242) 242 pixel clocks = 5.04 ? s p 2 frame end blanking (2 + reg0x05 - 19) (min reg0x05 value = 19) 2 pixel clocks = 0.042 ? s 2 q = p 1 + p 2 horizontal blanking (244 + reg0x05 - 19) (min reg0x05 value = 19) 244 pixel clocks = 5.08 ? s 2 a + q row time ((reg0x04 + 1) + (244 + reg0x05 - 19)) 1,524 pixel clocks = 31.75 ? s v vertical blanking (reg0x06 + 1) x (a + q) (min reg0x06 value = 15) 39,624 pixel clocks = 825.5 ? s n rows x (a + q) frame valid time (reg0x03 + 1) x (a + q) 1,560,576 pixel clocks = 32.51ms f total frame time (reg0x03 + 1 + reg0x06 + 1) x (a + q) 1,600,200 pixel clocks = 33.34ms table 5: frame time ? long integration time parameter name equation (master clock) default timing v vertical blanking (long integration time) (reg0x09 C reg0x03) x (a + q) 39,624 pixel clocks = 82.5 ? s f total frame time (long integratio n time) (reg0x09 + 1) x (a + q) 1,600,200 pixel clocks = 33.34ms
mt9m001_ds rev. m pub. 5/15 en 13 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor serial bus description serial bus description registers are written to and read from the mt9m001 through the two-wire serial inter- face bus. the sensor is a two-wire serial in terface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the mt9m001 through the serial data (s data ) line. the s data line is pulled up to 3.3v off-chip by a 1.5k ? resistor. either the slave or master device can pull the s data line down?the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? the slave device eight-bit address ? a(an) (no) acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's eigh t-bit address. the last bit of the address determines if the request will be a read or a write, where a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. the mt9m001 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register ad dress is automatically incremented, so that the next 16 bits are written to the next regi ster address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data eight bits at a time. the mast er sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high.
mt9m001_ds rev. m pub. 5/15 en 14 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor serial bus description stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of seven bits of address and 1 bit of direction. a ?0? (0xba) in the ls b (least significant bit) of the address indi- cates the write mode, and a ?1? (0xbb) indicates read mode. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred eight bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
mt9m001_ds rev. m pub. 5/15 en 15 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor two-wire serial interface sample write and read sequences two-wire serial interface sample write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 8. a start bit given by the master, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each eight-bit transf er, the image sensor will give an acknowl- edge bit. all 16 bits must be written before th e register will be updated. after 16 bits are transferred, the register addres s is automatically incremented so that the next 16 bits are written to the next register. the master st ops writing by sending a start or stop bit. figure 8: timing diagram showing a write to reg0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 9. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data eight bits at a time. the master sends an acknow ledge bit after each eight-bit transfer. the register address should be incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 9: timing diagram showing a re ad from reg0x09; returned value 0x0284 sclk s data start ack 0xba addr ack ack ack stop reg0x09 1000 0100 0000 0010 sclk s data start ack 0xba addr 0xbb addr 0000 0010 reg0x09 ack ack ack stop 1000 0100 nack
mt9m001_ds rev. m pub. 5/15 en 16 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor feature description feature description signal path the mt9m001 signal path consists of two stages, a programmable gain stage and a programmable analog offset stage. programmable gain stage a total programmable gain of 15 is available and can be calculated using the following formula: gain 1 to 8: gain = (bit[6] + 1) x (bit[5:0] x 0.125) for gain higher than eight, the user would need to set bit[6:5] = 11 and use the lower 3 lsb's bit[2:0] to set the higher gain values. the formula for obtaining gain greater than eight is as follows: total gain = 8 + bit[2:0] for example, for total gain = 12, the value to program is bit[6?0] = 1100100. the maximum total gain = 15, i.e. bit[6:0] = 1100111. the gain circuitry in the mt9m001 is designed to offer signal gains from one to 15. the minimum gain of one corresponds to the lowest setting where the pixel signal is guaran- teed to saturate the adc unde r all specified operating conditions. any reduction of the gain below this value may cause the sensor to saturate at adc output values less than the maximum, under certain conditions. it is recommended that this guideline be followed at all times. since bit[6] of the gain registers are multipli cative factors for the gain settings, there are alternative ways of achieving certain gains. some settings offer superior noise perfor- mance to others, despite the same overall gain. recommended gain settings are listed in tabl e 6. figure 10: signal path table 6: recommended gain settings at 48 mhz nominal gain increments recommended settings 1 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9 to 15 1.0 0x61 to 0x67 x + pixel output (signal minus reset) offset correction voltage (reg0x60, reg0x61, reg0x63, reg0x64) (signed lower 9 bits) x 2mv 10-bit adc adc dat a (9:0) gain selection (reg0x2b - 0x2e)
mt9m001_ds rev. m pub. 5/15 en 17 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor feature description programmable analog offset stage the programmable analog offset stage corrects for analog offset that might be present in the analog signal. the user would need to program register 0x62 appropriately to enable the analog offset correction. the lower eight bits (bit[7:0]) determines the absolute value of the analog offset to be corrected and bit[8] determines the sign of the correction. when bit[8] is ?1?, the sign of the correction is negative and vice versa. th e analog value of the correction relative to the analog gain stage can be dete rmined from the following formula: analog offset (bit[8] = 0) = bit[7:0] x 2mv analog offset (bit[8] = 1) = - (bit[7:0] x 2mv) column and row mirror image by setting bit 14 of reg0x20, the readout order of the columns will be reversed, as shown in figure 11. figure 11: readout of six columns in normal and column mirror output mode by setting bits 15 of reg0x20 the readout orde r of the rows will be reversed, as shown in figure 12. figure 12: readout of six rows in normal and row mirror output mode column and row skip by setting bit 3 of reg0x20, only half of the columns set will be read out. an example is shown in figure 13. only columns with bit 1 equal to ?0? will be read out (xxxxxxx0x). the row skip works in the same way and will on ly read out rows with bit 1 equal to ?0.? row skip mode is enabled by setting bit 4 of reg0x20. for both row and column skips, the number of rows or columns read out will be half of what is set in reg0x03 or reg0x04, respectively. d out 9?d out 0 line_valid normal readout col0 (9:0) col1 (9:0) col2 (9:0) col3 (9:0) col4 (9:0) col5 (9:0) d out 9?d out 0 reverse readout col5 (9:0) col4 (9:0) col3 (9:0) col2 (9:0) col1 (9:0) col0 (9:0) d out 9?d out 0 frame_valid normal readout row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) d out 9?d out 0 r everse readout row4 (9:0) row5 (9:0) row3 (9:0) row2 (9:0) row1 (9:0) row0 (9:0)
mt9m001_ds rev. m pub. 5/15 en 18 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor feature description figure 13: readout of eight pixels in normal and column skip output mode black level calibration the mt9m001 has automatic black level calibr ation on-chip which can be overridden by the user, as described below and shown in figure 14. the automatic black level calibration measures the average value of 256 pixels from two dark rows of the chip for each of the four co lors. the pixels are averaged as if they were light-sensitive and passed through the appropri ate color gain. this average is then digi- tally filtered over many frames. for each color, the new filtered average is compared to a minimum acceptable level (to screen for too low a black level) and a maximu m acceptable level. if the average is lower than the minimum acceptable level, the offs et correction voltage for that color is increased by one offset lsb (offset lsbs do not match adc lsbs; typically, one offset lsb is approximately 2mv). if it is above the maximum level, the level is decreased by 1 lsb (2mv). the upper threshold is automa tically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. this prevents black level oscillation from below the minimum to above the maximum. the lower threshold is increased with the maximum gain setting according to the formula described under reg0x5f. this prevents clipping of the black level. whenever the gain or any of the readout ti ming registers is changed (shutter width, vertical blanking, number of rows or columns, or the shutter delay) or if the black level recalculation bit, reset bit or restart bit is set, the running digitally filtered average is reset to the first average of the dark pixels. th e digital filtering over many frames is then restarted. whenever the gain or the readout timing registers are changed, the upper threshold is restored to its default value. after changes to the sensor configuration, la rge shifts in the black level calibration can result. to quickly adapt to this shift, a rapi d sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers. any changes to the registers listed above will ca use this recalculation. the data from this sweep allows the sensor to choose an accurate new starting point for the running average. this procedure can be disabled as described under reg0x5f. d out 9?d out 0 line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) g3 (9:0) r3 (9:0) d out 9?d out 0 line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0)
mt9m001_ds rev. m pub. 5/15 en 19 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor feature description figure 14: black level calibration flow chart x + pixel output (signal minus reset) offset correction voltage (color-wise) 10-bit adc adc data (9:0) gain selection (color-wise)
mt9m001_ds rev. m pub. 5/15 en 20 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor feature description still image capture with external synchronization in continuous mode video image capture, th e trigger signal should be held low or ?0.? to capture a still image, the sensor must first be put into snapshot mode by programming a ?1? in register 0x1e, bit 8. in snapshot mode, the sensor waits for a trigger signal (frame_valid, line_valid signals are low, pixel clock signal continues). when the trigger signal is received (active high), one frame is read out (a trigger signal can also be achieved by programming a restart?for example, program a ?1? to bit 0 of reg0x0b). the reset, readout ti ming for that frame will be the same as for a continuous frame with similar register sett ings; the only difference is that only one frame is read out. general timing for th e snapshot mode is shown in figure 15. figure 15: general timing for snapshot mode line_valid signal by setting bit 9 and 10 of reg0x20 the line valid signal can get three different output formats. the formats are shown when reading out four rows and two vertical blanking rows (figure 16). in the last format, the line_valid signal is the xor between the continuously line_valid signal and the frame_valid signal. figure 16: different line_valid formats trigger reset row 1 reset row reset row x strobe readout max strobe length (all rows integrating) min strobe length (1 row time) default frame_valid line_valid continuously frame_valid line_valid xor frame_valid line_valid
mt9m001_ds rev. m pub. 5/15 en 21 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor electrical specifications electrical specifications data output and propagation delays by default, the mt9m001 launches pixel da ta, frame_valid and line_valid with the rising edge of pixclk. the expectat ion is that the user captures d out [7:0], frame_valid and line_valid using the falling edge of pixclk. figure 17: data output timing diagram table 7: dc electrical characteristics (dc setup conditions: f clkin = 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, t a = 25c) symbol definition condition min typ max units v dd core digital voltage 3 3.3 3.6 v v aa analog voltage 3 3.3 3.6 v vaapix pixel supply voltage 3 3.3 3.6 v v ih input high voltage v pwr - 0.3 v pwr + 0.3 v v il input low voltage -0.3 0.8 v i in input leakage current no pull-up resistor; v in = v dd or d gnd -15 15 ? a v oh output high voltage v pwr - 0.2 v v ol output low voltage 0.2 v i oz tri-state output leakage current 15 ? a i dd digital operating current 20 24 ma i aa analog operating current 85 110 ma i aapix pixel supply current 5 10 ma clkin pixclk t r t f t clkin data[0-7] frame valid/ line valid xxx xxx xxx xxx xxx xxx note: frame_valid leads line_valid by 242 pixclks. note: frame_valid trails line_valid (1+ reg0x05-19) pixclks. t cp t pfl t pll t fvs t pd t oh p 0 p 1 p 2 p n t lvs t os t pfh t plh t
mt9m001_ds rev. m pub. 5/15 en 22 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor electrical specifications . note: 1 stresses greater than those listed may cause perm anent damage to the device. this is a stress rating only, and functional operation of the devi ce at these or any other conditions above those indicated in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect reliability. i stdbyd digital standby current stdby = v dd , clkin = 0 mhz 9 20 ? a i stdbyd w /clk digital standby current stdby = v dd , clkin = 48 mhz 55 125 ? a i stdbyda analog standby current stdby = v dd 80 100 ? a table 8: ac electrical characteristics (ac setup conditions: f clkin= 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, output load = 30pf, t a = 25c)) symbol definition condition min typ max unit f clkiin input clock frequency 1 48 mhz t clkin input clock period 1000 20.83 ns t pixclk period 1000 20.83 ns t r input clock rise time 4 v/ns t f input clock fall time 4 v/ns clock duty cycle 45 50 55 % t cp clkin to pixclk propagation delay 10 ns t pd pixclk to data valid 1 ns t pfh pixclk to fv high 7 ns t plh pixclk to lv high 7 ns t pfl pixclk to fv low 13 ns t pll pixclk to lv low 13 ns t os setup time for data before falling edge of pixclk t/2 -1 t/2 t/2 +1 ns t oh hold time for data after falling edge of pixclk t/2 -1 t/2 t/2 +1 ns t fvs setup time for fv before falling edge of pixclk 2 3 ns t lvs setup time for lv before falling edge of pixclk 2 3 ns c load load capacitance 30 pf table 9: absolute maximum ratings symbol parameter rating unit min max t op operating temperature 0 70 c t stg 1 storage temperature C40 125 c table 7: dc electrical ch aracteristics (continued) (dc setup conditions: f clkin = 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, t a = 25c) symbol definition condition min typ max units
mt9m001_ds rev. m pub. 5/15 en 23 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor electrical specifications two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 18: serial host interface start condition timing figure 19: serial host interface stop condition timing note: all timing are in units of master clock cycle. figure 20: serial host interface data timing for write note: s data is driven by an off-chip transmitter. figure 21: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. sclk 5 s data 4 sclk 5 s data 4 sclk 4 s data 4 sclk 5 s data
mt9m001_ds rev. m pub. 5/15 en 24 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor electrical specifications figure 22: acknowledge signal timing after an 8-bit write to the sensor figure 23: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. sclk sensor pulls down s data pin 6 s data 3 sclk sensor tri-states s data pin (turns off pull down) 7 s data 6
mt9m001_ds rev. m pub. 5/15 en 25 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor electrical specifications quantum efficiency figure 24: quantum efficiencymonochrome image center offset and orientation figure 25: image center offset 0 10 20 30 40 50 60 350 450 550 650 750 850 950 1050 quantum efficiency (%) wavelength (nm) quantum efficiency - monochrome pad 1 pixel (0,0) die center image center 7.75mm pixel array 0.015mm 0.712mm pixel (12, 20) black and boundary pixels 7.75mm
mt9m001_ds rev. m pub. 5/15 en 26 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor electrical specifications notes: 1. x and y coordinates referenced to center of die. 2. die center = package center. 3. image center offset from package center (x = 0.015mm, y = 0.712mm). figure 26: optical orientation table 10: optical area dimensions optical area pixel x-dimension y-dimension sxga center of pixel (20, 12) 3,340.70 ? m 3,372.45 ? m center of pixel (1299, 1035) -3,315.2 ? m -1,952.35 ? m chip size, mm (including seal ring) 7.75mm 7.75mm up pin 1 pixel array top of board bottom of board
mt9m001_ds rev. m pub. 5/15 en 27 ?semiconductor components industries, llc,2015 mt9m001: 1/2-inch megapixel digital image sensor electrical specifications figure 27: 48-pin clcc package outline drawing notes: 1. all exposed metallized area shall be gold plated 60 micro inches min thk. over nickel plated unless otherwise specified in purchase order. 2. seal area and die attach area shall be without metallization. 3. die center to package center accuracy +/- 100 ? m. 4. die thickness = 0.675mm(26.5mils). 5. epoxy thickness for die attachment is 0.025~0.050 mm. 6. glass transmittance >=90%. 7. glass tilt =0.10mm max. 8. all dimensions in millimeters. top view side view bottom view
mt9m001_ds rev. m pub. 5/15 en 28 ?semiconductor components industries, llc,2015. mt9m001: 1/2-inch megapixel digital image sensor revision history revision history rev. m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/15 ? updated ?ordering information? on page 2 rev. l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/15 ? converted to on semiconductor template rev. k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/2/11 ? removed digital clarity ? applied updated template rev. j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to non-confidential rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? removed registers and transfered to separate document rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/09 ? updated figure 27: ?48-pin clcc package outline drawing? on page 30 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/09 ? updated to aptina template rev e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/06 ? updated description in table 2, ?available part numbers,? on page 1 ? update figure 4: ?pixel pattern detail (top right corner),? on page 9 ? updated "data output and propagation delays" on page 21 ?updated t pfl and t pll in table 8, ?ac electrical characteristics,? on page 22 rev d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/06 ? updated table 1, ?key performance parameters,? on page 1 ? update table 2, ?available part numbers,? on page 1 ? updated figure 4: ?pixel pattern de tail (top right corner),? on page 9 rev c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/05 ? remove color information ? updated table 1, ?key performance parameters,? on page 1 ? updated table 6, ?register list and default values,? on page 11 ? updated table 7, ?registe r description,? on page 12 ? updated figure 12, readout of six rows in normal and row mirror output mode, on page 17 ? deleted figure 13, readout of eight pixels in normal and column skip output mode, on page 18 ? updated table 8, ?ac electrical characteristics,? on page 22 ? updated figure 25, image center offset, on page 25 ? updated figure 27, 48-pin clcc package outline drawing, on page 27 rev b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/05 ? page 1, remove preliminary disclaimer ? page 1, add key performance parameters table, add applications ? page 2, add table of contents ? page 6, update pin description table
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